1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and, more specifically, to the design of copper based interconnections in sub-micron dimensions with reduced sensitivity for corrosion and defects, and thereby, with improved reliability. The invention also relates to providing methods for forming the designed structure.
2. Description of Related Art
As device geometry continues to scale down for Ultra Large Scale Integrated circuits, there is a growing demand for an interconnect wiring with minimum pitch and high conductivity, and, for a passivation material with a low dielectric constant, while requiring a more robust reliability than ever before. In particular, in the regime of sub-quarter micron line width, the factors of paramount importance are high electrical conductivity and high electromigration resistance.
One approach has been to use copper metallurgy, for its high conductivity and high electromigration resistance, along with polyimide passivation for low cross capacitance. A process utilizing this approach is disclosed by Luther et al. in VLSI Multilevel Interconnection Conference (VMIC), pp.15-21, 1993. Further process improvement, using a double damascene method to simultaneously form copper interconnection lines and inter-level via-studs, is taught by Dalal et al. in U.S. Pat. No. 5,434,451, of common assignee with the present application. Damascene methods involve filling of narrow trenches or narrow holes or a combination of both. It is well known in the art that the use of Physical Vapor Deposition (PVD) methods such as sputtering or evaporation to fill such narrow holes and trenches is not suitable because a highly tapered cross section of the filled metal lines or studs is formed. Joshi et al. in U.S. Pat. No. 5,300,813, also of common assignee with the present application, teaches using PVD methods to deposit the high conductivity metal followed by Chemical Vapor Deposition (CVD) of a tungsten cap layer to fill up the top part of the tapered cross section. This capping process results in substantial reduction in cross-sectional area of copper conductor because of the tapered cross-section. Also, because the capping metal is deposited along with the conductor metal, slits of conductor metal are exposed along the conductor edges in the finished product. Further, during the chemical-mechanical polishing step in this capping process, the hard metal particles removed by polishing tend to abrade the metal line. Therefore, conformal deposition methods such as CVD or electroplating are required for copper deposition.
However, it has been found that CVD copper suffers from limited shelf life of the highly complex precursors required. A more serious problem with CVD copper is the contamination of manufacturing line by vapors of copper precursor, which poison the semiconductor devices.
Copper deposition by electroplating has been in use for Printed Circuit Board (PCB) for decades. Because of its low cost, low deposition temperature and its ability to conformally coat narrow openings, electroplating is a preferred method of deposition in copper interconnections. It should be understood that electroplating of copper requires a copper seed layer on the substrate. Invariably, a PVD method has been used to deposit copper for seed layer. However, it has been found that PVD deposited copper has ten times lower electromigration resistance, as compared to electroplated copper; and three times lower electromigration resistance, as compared to CVD copper. Because the copper seed layer may form up to 20% of the cross-sectional area of an interconnect line, this seed layer seriously hampers the electromigration characteristic of copper interconnection. Whereas the electromigration resistance of copper is high enough to sustain the wear-out in normally designed conductor lines, defect-induced electromigration failures have been observed in the PVD seed layer/electroplated copper conductor lines. Because of the high conductivity of copper, line defects such as conductor line width or thickness, when thinned down to a couple of hundred angstroms, are able to pass undetected through the electrical screen tests. Understandably, current density in these regions is considerably high during actual use, thereby causing early field fails due to electromigration.
Another major problem in using a PVD method for seed layer arises when interconnection lines are of sub-quarter-micron dimensions. Here, even a thin seed layer deposited by PVD technique, considerably narrows down the opening as mentioned above. This results in a hollow shelled line.
CVD copper deposition techniques present problems, for example, contamination of the manufacturing line by vapors of copper precursor, thereby poisoning the semiconductor devices. The greater the thickness of CVD deposited copper, the greater is the propensity for line contamination.
Co-deposition of various elements with copper for high temperature application or for improving the mechanical strength is taught by Thomas in U.S. Pat. No. 5,414,301; by Shapiro et al. in U.S. Pat. No. 4,007,039; Akutsu et al. in U.S. Pat. No. 4,872,048; and, by Woodford and Bricknell in U.S. Pat. No. 4,406,858. However, when copper is co-deposited with another element, the electrical resistivity usually increases, which defies the very purpose of using copper in high performance systems.
Yet another reliability concern in copper metallurgy is corrosion. This is described below with the help of illustrations in FIGS. 1 and la. FIG. 1 is part of a structure of the above described interconnect scheme of the prior art, showing two levels of metal interconnections, each level defined by a double damascene method. FIG. 1a is an enlarged view of cross-section of an interconnect; wherein, copper interconnect line 9 on one level is shown making contact to lower level metal interconnect line 102 through via-stud 11. It should be understood that in a double damascene method the via stud 11 and the conductor line 102 are an integral part of one another. The copper interconnect comprises an adhesive layer 5, an optional barrier layer 6; a PVD copper seed layer 8; bulk copper layer 9 and 11, and an inorganic insulator 4 atop polyimide insulator 3.
It has been found that corrosion of copper lines generally takes place in association with the use of polyimide for interlevel insulation. This is because whenever polyimide is used for interlevel insulation its application usually involves addition of a thin layer of inorganic insulator 4. This thin layer of inorganic insulator is added either to act as an etch stop, as taught in U.S. Pat. No. 4,789,648 to Chow et al., or to reduce polyimide debris formation during chemical-mechanical polishing, as taught by Joshi et al. in U.S. Pat. No. 5,403,779 (both patents assigned to the instant assignee). The deleterious effect of this inorganic insulator layer 4 is that it prevents escape of the residual moisture in the polyimide film. Consequently, vapor pressure builds up in polyimide film, which finds a path to the copper. As a result, copper oxides and hydroxides are formed. With time and temperature, these oxides and hydroxides ultimately result in formation of voids 13 (FIG. 1) in the copper conductor. These corrosion induced voids 13 are believed to initiate from the top surface of the copper conductor for two reasons. One, liner layers 5 and 6 cover the bottom and sides of the conductor lines, but not the top surface. Second, junctions between the inorganic insulator layer 4 and the liner 5 and 6 on the conductor line side walls become disjointed during process temperature excursions, thereby providing a path for moisture to come in contact with copper. Joshi et al. U.S. Pat. No. 5,426,330, assigned to the instant assignee, teaches a method of providing a tungsten cap atop the copper conductor to prevent copper corrosion. As discussed earlier, this capping method forms undesirable metal debris during polishing, causing metal line abrasion.
Thus, despite repeated efforts, and various schemes in the prior art, manufacturing problems due to defect sensitive electromigration failure and corrosion remain. Better methods for making copper integrated circuit pattern with improved reliability and reduced defect sensitivity need to be developed.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for fabricating high performance interconnection circuitry of sub-half-micron dimension with improved process yield and reliability.
Another object of the present invention is to provide a high conductivity copper based metallurgy with low dielectric constant polyimide passivation.
It is yet another object of the present invention to reduce defect sensitivity of copper interconnect metallurgy by improving its electromigration resistance.
It is still another objective of the present invention to provide electroplated copper interconnection lines with reduced PVD copper seed layer thickness to improve the electromigration resistance of the interconnect line.
It is a further object of the present invention to provide a method of metal capping copper lines which does not affect the metal line integrity.